1. Field of the Invention
The present invention relates to a semiconductor integrated circuit provided on a semiconductor chip, and in particular, to a semiconductor integrated circuit operable in synchronization with an external clock signal supplied from outside the semiconductor chip.
2. Description of the Related Art
Conventionally, in a structure in which a semiconductor integrated circuit formed on a semiconductor chip operates in synchronization with an external clock signal supplied from outside the semiconductor chip, a synchronization circuit such as a PLL (Phase-Locked Loop) circuit is used for outputting an internal clock signal in synchronization with the external clock signal. The internal clock signal output by the synchronization circuit is supplied to a plurality of functional blocks formed on the semiconductor chip.
However, it is difficult to completely uniformalize the distances between the synchronization circuit and each of the plurality of functional blocks due to various constrains in laying out the synchronization circuit and the plurality of functional blocks on the semiconductor chip. In the case where the distances between the synchronization circuit and each of the plurality of functional blocks are different from one another, the transfer delays of the internal clocks to the functional blocks vary. Such differences generate a skew of the internal clock signal. The higher the frequency of the external clock signal is, the more serious the skew is.